Carrier Phase Synchronization for QPSK Using Differential Encoding/Decoding
Introduction
In the previous
QPSK Simulink Exercise the phase of the
unmodulated carrier was assumed known.
Unfortunately, this is not the case in practice.
The carrier phase is unknown and must be extracted from the received signal using
a carrier phase recovery subsystem.
In this exercise, you will design a PLL-based carrier phase recovery subsystem for
QPSK which will be used to process QPSK modulated data contained in the file qpskcrdedata.mat
To deal with the 90-degree phase ambiguity of the PLL-based carrier phase synchronizer,
this exercise uses differential encoding.
In differential encoding, the 2-bit quaternary symbols defined the phase
shift of the modulated carrier instead of the absolute phase of the
modulated carrier.
That is each symbol maps to one of the four possible phase shifts (0, 90, 180, 270) degrees.
The detector is based on a conventional coherent QPSK detector followed by a
differential decoder.
Because the phase ambiguity does not alter the phase shift from one symbol
to the next, the decoded symbols are the correct symbols.
In this way, differential encoding/decoding is transparent to the 90 degree phase
ambiguity.
Textbook References
M-ary QAM: Section 5.3,
discrete-time realizations: Section 5.3.2,
partial response pulse shapes: Section A.2,
discrete-time PLL: Section C.2,
carrier phase synchronization for QPSK: Section 7.2,
differential encoding for phase ambiguity resolution for QPSK: Section 7.7.2.
Specifications
|
normalized sample rate: |
8 samples/symbol |
normalized carrier frequency: |
0.3 cycles/sample |
carrier phase: |
unknown |
average energy: |
2 |
pulse shape: |
SRRC (50% excess bandwidth, span = 12 symbols) |
symbol clock offset: |
0 |
input file |
qpskcrdedata.mat |
phase ambiguity resolution |
differential encoding |
|
bits phase shift
------------------
00 0 deg
01 90 deg
10 -90 deg
11 180 deg
|
input message length: |
1092 symbols (2184 bits or 312 ASCII characters) |
SYNC | 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 |
|
|
the frame format is shown below
The packet is repeated 4 times to allow your PLL to acquire and lock.
|
Design the Detector
Design the detector, shown below, using blocks from the Simulink, DSP System,
and Communications System Toolboxes.
I recommend you start with the detector from the
QPSK Carrier Phase Synchronization Simulink Exercise
and make changes as necessary.
Design the loop filter to create a second order loop to the following specifications:
closed-loop equivalent noise bandwidth = 0.02 (normalized to the symbol rate),
damping factor = 0.7071.
Exercise
-
For the detector input, use the From File block and set the
Filename to qpskcrdedata.mat and set the sample time to 1.
-
Set the simulation parameters as follows:
Simulation Time |
Start time: 0.0 |
Stop time: (12+(8+1092)*4)*8-1 |
Solver selection |
Type: Fixed-step |
Solver: discrete (no continuous states) |
-
Run the simulation.
-
The detector produces 4412 symbol estimates.
Even though the SYNC and DATA fields are repeated four times,
the PLL does not lock until part way through the sample sequence.
-
To find the data symbols, look for the 16-bit (8 symbol) synchronization pattern (SYNC)
in the differential decoder output.
(You will likely find it more than once.)
The 1092 symbols following the SYNC correspond to 312
7-bit ASCII characters.
-
Determine the message using either your Matlab script or an
ASCII Table.
-
Plot the phase error (loop filter output) and use this plot to estimate
how long (measured in bits) it took your PLL to lock.
-
Plot the eye diagram and de-rotated signal space projections.