A Complete QPSK System
Introduction
The previous QPSK Simulink exercises assumed perfect synchronization,
perfect timing synchronization, or perfect phase synchronization.
It is now time to explore how it is in practiceneither carrier phase nor
timing is known to the detector and must be estimated.
Simultaneous carrier phase and symbol timing synchronization is an example
of a
joint estimator: more than one unknown parameter is estimated.
This is accomplished using two PLLs, one for timing synchronization (the inner loop) and
one for carrier phase synchronization (the outer loop).
The issue of carrier phase ambiguity is still with us, so differential encoding is also
used here.
In this exercise, you will design a joint carrier phase ans symbol timing timing synchronizer
for QPSK based on two PLLs.
There are three sample rates in play in this design, so you must be careful in assigning
sample times to the Simulink blocks.
The detector, with its accompanying bit timing synchronizer, will be used to process
the modulated sampled in the file qpskcompletedata.mat.
Textbook References
Mary QAM: Section 5.3,
discretetime realizations: Section 5.3.2,
partial response pulse shapes: Section A.2,
discretetime PLL: Section C.2,
carrier phase synchronization for QPSK: Section 7.2,
differential encoding for phase ambiguity resolution for QPSK: Section 7.7.2,
general discussion of timing synchronization: Section 8.1,
discretetime techniques for symbol timing synchronization for binary PAM:
Section 8.4,
discretetime techniques for symbol timing synchronization for MQAM:
Section 8.5.
Specifications

normalized sample rate: 
8 samples/bit 
normalized carrier frequency: 
0.3 cycles/sample 
carrier phase 
unknown!! 
average energy: 
1 
pulse shape: 
SRRC (50% excess bandwidth, span = 12 symbols) 
symbol clock offset: 
unknown!! 
input file 
qpskcompletedata.mat 
phase ambiguity resolution 
differential encoding 

bits phase shift

00 0 deg
01 90 deg
10 90 deg
11 180 deg

packet format: 
PRE = 2000 bits (you don't need to know what they are)
SYNC = 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
DATA = 3206 bits




Preliminary Design
Design the Detector
Design the detector, shown below, using blocks from the Simulink, DSP System,
and Communications System Toolboxes.
Design both loop filters to create a second order loops to the following specifications:
closedloop equivalent noise bandwidth = 0.01 (normalized to the symbol rate),
damping factor = 0.7071.
Design Notes

Because I plan on using the earlylate detector for the timing error detector (TED)
and the earlylate TED operates at 2 samples/symbol, the matched filter output
output is downsampled by 4.
The matched filter and its input operate at 8 samples/symbol: the downsampled sequence
is at 2 samples/symbol.

The carrier phase synchronization loop is the outer loop shown in red.

In the two previous two Simulink exercises devoted to carrier phase
synchronization for QPSK
(Carrier Phase Synchronization for QPSK Using the Unique Word
and
Carrier Phase Synchronization for QPSK Using Differential Encoding/Decoding),
perfect timing synchronization was assumed and this assumption allowed the carrier phase
PLLs to operate at one sample per symbol.

In contrast, the matched filter outputs here are at 2 samples/symbol.
Consequently, the CCW rotation block operates at 2 samples/symbol.

The PED operates at 2 samples/symbols, but only updates at 1 sample/symbol.
This is why the PED needs to strobe input.
So, when the strobe is asserted, the PED output follows the formula (7.26) on page 343.
When the strobe is not asserted, the PED output is 0.
(For those of you familiar with multirate discretetime processing, this is like an
upsamplebytwo operation.)

The loop filter and DDS operate at 2 samples/symbol.
(In the context of multirate processing, the PED does the upsamplebytwo and the loop filter
is the "interpolating filter" to smooth out the inserted zeros.)

The symbol timing PLL is the inner loop shown in blue.
Except for the CCW rotation block, the symbol timing PLL is identical to the one
you designed for the
Symbol Timing Synchronization for QPSK
Simulink Exercise.

Use a Farrow interpolator.
You can use either the piecewiseparabolic version (see the top of Figure 8.4.17
on p. 437) or the cubic version (see the bottom of Figure 8.4.18
on p. 438).

The strobe signal is derived from the decrementing modulo1 counter.
Use the underflow condition in the decrementing mod1 counter as the
strobe signal.

You need to create an "enabled" version of the earlylate TED.
When the strobe is high, the TED output is given by equation (8.34) on page 420.
When the strobe is low, the TED output is zero.

For interpolation control, use the decrementing modulo1 counter described in
Section 8.4.3 (pp. 441  444).

The "enabled hold" block outputs the previous value when the strobe
is low, or passes the input to the output when the strobe is high.
This block is needed because the fractional interval is updated by the mod1
counter only once per symbol, but the interpolator operates at 2 samples/symbol.
The hold operation ensures that the interpolator is using the proper value for
the fractional interval.
Simulink provides a skeletal enabled subsystem:
Simulink > Ports & Subsystems > Enabled Sybsystem
The default enabled subsystem is shown below
The subsystem consists of a simple wire with the enable icon above it.
This means the wire is only active when the enable signal (strobe in this case)
exceeds a predefined threshold (double click on the enable block to set the threshold).
When the enable signal (strobe in this case)
is below the predefined threshold, nothing happens and the output holds its value.

The decision subsystem is also enabled.
This is because decisions should be made on every other interpolator output on average.
The strobe indicates which interpolator outputs
represent the desired signal space projections.
An example of the enabled decision subsystem for binary PAM is shown below
Exercise

Incorporate the carrier phase and symbol timing synchronization PLLs into a QPSK detector.

For the detector input, use the From File block and set the
Filename to qpskcompletedata.mat and the sample time to 1.

Set the simulation parameters as follows:
Start Time: 
0.0 
Stop Time: 
8*(2611+24) 
Solver Options
Type: 
Fixedstep 
Solver: 
discrete (no continuous states) 
Fixed step size: 
auto 
Tasking and sample time options
Periodic sample time constraint: 
Unconstrained 
Treat each discrete state as a separate task: 
Deselect 

Run the simulation.

The detector produces approximately 2625 symbol decisions.
(The exact number depends on the number of times the strobe is high.
This, in turn, depends on the dynamics of your symbol timing PLL.)
 To find the data, look for the 16 bit SYNC pattern in the detector output.
Once you find it, the following 3206 bit decisions correspond to 458
7bit ASCII characters.
Determine the message using either your Matlab script or an
ASCII Table.

Plot the filtered phase error (loop filter output) and use this plot to estimate
how long (measured in symbols) it took for your carrier phase PLL to lock.

Plot the filtered timing error (loop filter output) and use this plot to estimate
how long (measured in symbols) it took for your timing PLL to lock.

Plot the fractional interpolation interval (mu). What conclusions can you
make based on this plot?